1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a static random access memory (SRAM).
2. Description of the Related Art
Large-scale logic LSI includes semiconductor memory devices to temporarily store data. As the scales of systems have recently been increased, automatically-designed logic circuit blocks include a large number of SRAM on a large scale. The SRAM preferably include as few interconnection layers as possible to improve compatibility with designs using the automatic placement and routing.
Conventional SRAM memory cell arrays include memory elements such as memory cells disposed in an array. Each memory cell has a pair of storage nodes that are complementary to each other. A pair of bit-lines is connected to the pair of storage nodes, respectively. Each of the bit-line is connected to a write circuit and a read circuit. When an address signal is input to the semiconductor memory device, an address decoder selects one word-line. The write and read circuits then write/read data from the memory cell connected to the word-line. Data is written/read via the bit-line pair.
In the semiconductor memory device, the bit-line pair is connected to a large number of memory cells. The capacitance load of the bit-line pair is largely increased by the capacitance of the terminals connected to the memory cell storage nodes and the capacitance of the interconnections.
In view of miniaturization, each memory cell includes a small-sized transistor having low driving ability. Each memory cell thus sends only small signals to the bit-lines. Each of the write and read circuits thus includes a sense amplifier to amplify the small amplitude difference between the bit-lines. In the read operation, the bit-lines are set (precharged) at the ‘H’ level. Data is read from the memory cell as the change of the bit-line level. In the write operation, depending on the write data, one of the bit-lines precharged is driven to the ground level. Data is thus written to the memory cell.
In conventional SRAM, the differential sense amplifier detects the small potential difference. Performance dispersion of the devices used in the differential circuit may cause malfunction. Recent decrease of the device size increases the dispersion of the device performance. Additionally, recent decrease of the operating voltage reduces the margin of the potential difference. During the reading operation, both bit-lines are almost kept at the ‘H’ level. The memory cell having an unstable operating point due to the device dispersion may thus have its data broken.
JP 2002-100187 describes a semiconductor memory device that includes hierarchical bit-lines to reduce their capacitance load without increasing the device area. In the semiconductor memory device described in JP 2002-100187, the memory cell array is divided into a plurality of sub arrays. The bit-lines are hierarchized into a pair of local bit-lines in each of the sub arrays and a global bit-line connected in common to the plurality of the sub arrays. A different pair of local bit-lines reside in each of the sub arrays and are connected to each of the memory cells therein The global bit-line is connected to each of the local bit-line pair. In the memory access, the address decoder selects a memory cell and a sub array including that memory cell. The local bit-lines in the selected sub array is connected to the global bit-line by a switching means. Data may thus be read or written. The capacitance of the memory cell terminals is decreased by a factor of number of the sub arrays. The total capacitance load is thus decreased, improving the operation frequency.
The semiconductor memory device described in JP 2002-100187 includes the hierarchical bit-lines to read data using a complementary metal oxide semiconductor (CMOS) circuit instead of the differential sense amplifier. This may reduce malfunction of the read circuit due to the memory cell dispersion. Unfortunately, the semiconductor memory device described in JP 2002-100187 includes the additional global bit-line, increasing the number of bit-lines per bit from two to three. Usually, the memory cell optimized to have the smallest area may include only two bit-lines. It is thus necessary to layout the global bit-line using a different interconnection layer. This increases the number of interconnection layers included in the SRAM circuit. The design using the automatic placement and routing technique should thus use one less interconnection layer in the SRAM circuit area than in the other areas.